EXPERIENCES
Summer 2025
Technology Design Co-Optimization Engineer Intern
Credo Semiconductor, San Jose
- Working on process node migration and RTL-to-GDSII flows for advanced semiconductor designs.
- Conducting signal analysis and DSP optimization for high-speed communication systems.
- Designing and testing SAR ADC architectures for precision analog-to-digital conversion.
- Implementing Synopsys pipelining techniques and integrating with MATLAB for system-level validation.
Fall 2024
Undergraduate Instructional Assistant
University of Massachusetts Amherst, Amherst
- Hosted biweekly office hours, supporting approximately 120 students on FPGA security labs and homework.
- Assisted with lab procedures, such as implementing a TRNG on the Altera Quartus Prime with Nios II scripting.
- Facilitated communication between students and professor, addressing concerns and ensuring smooth course delivery.
- Graded labs, homework, and exams, providing feedback to both course instructor and students.
Summer 2024
Foundry Engineer Intern
Credo Semiconductor, San Jose
- Simulated PAM4 channel in MATLAB with FFE/DFE equalization, visualizing eye openings and ADC slicer offset.
- Reduced PLL simulation times by 400% on Synopsys CC through Verilog-A scripting and Simulink co-simulation.
- Migrated SerDes designs from Cadence Virtuoso to Synopsys CC, translating Tcl automation scripts to Perl.
- Facilitated meetings with Synopsys & Mathworks Application Engineers, discussing co-simulation potential.
Fall 2023
Assistant Researcher
Emerging Embedded Technologies Lab, Amherst
- Researching capabilities of capturing Mixed Reality (MR) headset sensor data.
- Deployed MRTK, Photon Unity Networking, and MS Azure Spatial Anchors to create a collaborative MR environment.
- Scripted a C# program to capture headset data and relevant metrics into a CSV file for further analysis.
- Explored methods that adversaries could identify users based off of sensor readings.
Summer 2023
Cyber Security Engineer Intern
Deloitte & Touche, Taipei
- Assessed bias in blackbox AI Fintech tools using Veritas Toolkit 2.0, gaining expertise in finance AI system metrics.
- Automated internal social engineering test with Python, saving 30% time compared to conventional manual method.
- Translated NIST Ai frameworks to Chinese, using Excel and PowerPoint to quantify and propose ideas.
- Assisted in app development for startup clients, familiarizing with Android Studio, Gradle, and Google Maps API.
FEATURED PROJECTS
Efficient Dual ALU RISC-V Processor
This project involved designing and implementing a custom RISC-V processor with dual ALUs, allowing dynamic switching between high and low precision for optimal power efficiency. I developed a flexible datapath and control unit, and validated the design through comprehensive testbenches and SPICE simulations to ensure full compliance with the RV32I instruction set.
Cadence Virtuoso
Cadence Innovus
Synopsys Verdi
RISC-V
PulsePatch
PulsePatch is a wearable ECG device designed for real-time cardiac monitoring, with a focus on minimizing channel noise. I built a CNN-based classifier trained on the MIT-BIH dataset to detect arrhythmias, and engineered a portable, battery-powered system, carefully verifying power consumption and signal quality throughout development.
Android Studio
TensorFlow
KiCad
Embedded C
EDUCATION
University of Massachusetts Amherst
Bachelor of Science in Computer Engineering, 2021–2025
Relevant Coursework
TECHNICAL SKILLS
Languages
Python
MATLAB
C
Bash
SystemVerilog
Verilog
TCL
Perl
RISC-V
SQL
EDA Tools
Simulink
Synopsys
Cadence
ModelSim
KiCad
Synopsys Suite
Design Compiler
Custom Compiler (CC)
HSPICE
Verdi
Cadence Suite
Virtuoso
Pegasus
Innovus
Developer Tools
Android Studio
Adobe XD
MS Azure
Git
Quartus Prime
Other Technologies
JMP
Unity
Wireshark
Linux
RHEL8
TensorFlow