Kenneth Lin

01 / CAREER

Career

I’m a Computer Engineering master’s student at USC with experience in flow automation and high-speed circuit characterization. I’m drawn to the space where signal integrity meets digital implementation: high-speed connectivity, from RTL to silicon. Currently at Credo Semiconductor.

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Kenneth Lin
01

Experience

  • Delivered testbenches to characterize high-speed circuits across frequency, timing, and power metrics.
  • Optimized the Rx signal chain (CTLE, Sample & Hold, ADC) with ASO.ai to enhance signal integrity and performance.
  • Migrating a legacy Fusion Compiler flow to an advanced PDK, reading RTL designs and compiling NDMs with Tcl.
  • Developed a MATLAB-PrimeWave pipeline for automated waveform post-processing, accelerating schematic validation.
Fusion CompilerPrimeWaveMATLABTclASO.ai
  • Hosted biweekly office hours, supporting 120 students on FPGA security labs, quizzes, and homework.
  • Led lab exercises, implementing circuits on FPGAs and integrating with the Nios II processor in Quartus Prime.
  • Facilitated student-professor communication to resolve issues and ensure smooth course delivery.
  • Graded labs, homework, and exams, providing detailed feedback to students and instructor.
FPGAQuartus PrimeNios II
  • Simulated PAM4 channels in MATLAB with FFE/DFE equalization, analyzing eye openings and ADC slicer offset.
  • Reduced PLL simulation times by 400% on Synopsys CC through Verilog-A scripting and Simulink co-simulation.
  • Migrated SerDes designs from Cadence Virtuoso to Synopsys CC, translating Tcl automation scripts to Perl.
  • Coordinated with Synopsys and MathWorks application engineers on co-simulation workflows and tool integration.
MATLABSimulinkVerilog-ASynopsys CCTcl → Perl
  • Researched methods of capturing Mixed Reality (MR) headset sensor data.
  • Deployed MRTK, Photon Unity Networking, and MS Azure Spatial Anchors to create a collaborative MR environment.
  • Scripted a C# program to capture headset data and relevant metrics into CSV for analysis.
  • Explored how adversaries could identify users from sensor readings alone.
UnityMRTKC#Azure
02

Featured Projects

An SS-LMS adaptive 3-tap FFE / 1-tap DFE equalizer, closing timing at 50 MHz post-layout on SkyWater 130nm. RTL verified against MATLAB co-simulation with eye-diagram metrics and BER analysis; RTL-to-GDSII automated with Yosys and OpenROAD to a DRC-clean, timing-clean signoff.

MATLABVerilogYosys / OpenROADSkyWater 130nm

A 512-bit SRAM array with peripheral logic, reaching 1 GHz pre-layout simulation and 650 MHz post-layout. Hierarchical layout generation automated with SKILL scripting, minimizing area through custom cell abutment; verified through DRC/LVS sign-off with read/write test vector sequences.

Cadence VirtuosoSKILLDRC / LVS
03

Education

University of Southern California

M.S. in Computer Engineering · 2025 to Present

Relevant coursework

VLSI System DesignDigital Signal ProcessingIntegrated Memories

University of Massachusetts Amherst

B.S. in Computer Engineering · 2021 to 2025

Relevant coursework

VLSI DesignFPGA SecurityComputer ArchitectureEmbedded SystemsMachine Learning
04

Technical Skills

Languages

MATLABTclBashSystemVerilogPython

EDA Tools

Fusion CompilerSimulinkSynopsys Design CompilerSynopsys Custom CompilerHSPICECadence VirtuosoCadence InnovusPegasusModelSim

Developer Tools

GitQuartus PrimeAndroid StudioAdobe XD

Other

RHEL8TensorFlowUnityWiresharkJMPMS Office
05

Leadership

  • Coordinated and hosted weekly cooking sessions, directing a team of 20 members in an industrial-grade kitchen.
  • Scripted a Discord bot synced to Jira Cloud to automate task handling, pushing tasks with approaching deadlines.
  • Mapped out a $17,000 term budget to fund club events, ensuring efficient resource allocation.
Discord APIJira Cloud