Career — Kenneth Lin

Experience

Credo Semiconductor · San Jose, CA

Associate Design EngineerAug 2026 to Present

Middle/backend digital design flow.

Running the digital middle-end flow from design initialization through clock tree synthesis, routing, and chip finish.
Writing Tcl utilities for physical implementation, including IP-aware placement blockages and filler insertion, verified through DRC runs.

Fusion CompilerTclBashICV

Technology Design Co-Optimization Engineer InternJun 2025 to Aug 2026

High-speed mixed-signal validation.

Delivered power and timing reports across high-speed digital and AMS circuit blocks.
Debugged SAR ADC simulation migration across process nodes in Custom Compiler.
Enabled a Synopsys-to-MATLAB analysis pipeline with the MATLAB Engine API, replacing manual waveform exports with automatic post-simulation analysis.

Custom CompilerMATLABASO.ai

Undergraduate Instructional AssistantSep 2024 to Dec 2024

University of Massachusetts Amherst · Amherst, MAFPGA security labs and office hours.

Hosted biweekly office hours, supporting 120 students on FPGA security labs, quizzes, and homework.
Led lab exercises, implementing circuits on FPGAs and integrating with the Nios II processor in Quartus Prime.
Facilitated student-professor communication to resolve issues and ensure smooth course delivery.
Graded labs, homework, and exams, providing detailed feedback to students and instructor.

FPGAQuartus PrimeNios II

Foundry Engineer InternMay 2024 to Aug 2024

Credo Semiconductor · San Jose, CAPAM4 channel modeling, PLL co-simulation, and SerDes tool migration.

Simulated PAM4 channels in MATLAB with FFE/DFE equalization, analyzing eye openings and ADC slicer offset.
Reduced PLL simulation times by 400% on Synopsys CC through Verilog-A scripting and Simulink co-simulation.
Migrated SerDes designs from Cadence Virtuoso to Synopsys CC, translating Tcl automation scripts to Perl.
Coordinated with Synopsys and MathWorks application engineers on co-simulation workflows and tool integration.

MATLABSimulinkVerilog-ASynopsys CCTcl → Perl

Assistant ResearcherSep 2023 to Dec 2023

Emerging Embedded Technologies Lab · Amherst, MAMixed Reality sensor-data capture and user-identification research.

Researched methods of capturing Mixed Reality (MR) headset sensor data.
Deployed MRTK, Photon Unity Networking, and MS Azure Spatial Anchors to create a collaborative MR environment.
Scripted a C# program to capture headset data and relevant metrics into CSV for analysis.
Explored how adversaries could identify users from sensor readings alone.

UnityMRTKC#Azure

Cyber Security Engineer InternSummer 2023

Deloitte & Touche · Taipei, TaiwanAI-bias detection for fintech tools and a Python-automated social engineering test.

Detected bias in AI-driven finance management tools with Veritas Toolkit 2.0, deploying it across public AI fintech systems such as credit scoring models.
Exported and containerized models for seamless integration with the Veritas tool.
Presented findings to audit and solutions teams, shaping how to quantify the metrics and next steps for AI governance in finance.
Automated the annual internal social engineering test with Python, covering roughly 400 employees and cutting completion time by 30% versus the manual method.

Veritas Toolkit 2.0PythonContainerization

Featured Projects

An SS-LMS adaptive 3-tap FFE / 1-tap DFE equalizer, closing timing at 50 MHz post-layout on SkyWater 130nm. RTL verified against MATLAB co-simulation with eye-diagram metrics and BER analysis; RTL-to-GDSII automated with Yosys and OpenROAD to a DRC-clean, timing-clean signoff.

Eye diagrams, before and after equalization

MATLABVerilogYosys / OpenROADSkyWater 130nm

A 512-bit SRAM array with peripheral logic, reaching 1 GHz pre-layout simulation and 650 MHz post-layout. Hierarchical layout generation automated with SKILL scripting, minimizing area through custom cell abutment; verified through DRC/LVS sign-off with read/write test vector sequences.

Digital verification with a custom testbench

Cadence VirtuosoSKILLDRC / LVS

Education

University of Southern California

M.S. in Computer Engineering · 2025 to Present

Relevant coursework

VLSI System DesignDigital Signal ProcessingIntegrated Memories

University of Massachusetts Amherst

B.S. in Computer Engineering · 2021 to 2025

Relevant coursework

VLSI DesignFPGA SecurityComputer ArchitectureEmbedded SystemsMachine Learning

Technical Skills

Languages

MATLABTclBashSystemVerilogPython

EDA Tools

Fusion CompilerSimulinkSynopsys Design CompilerSynopsys Custom CompilerHSPICECadence VirtuosoCadence InnovusPegasusModelSim

Developer Tools

GitQuartus PrimeAndroid StudioAdobe XD

Other

RHEL8TensorFlowUnityWiresharkJMPMS Office

Leadership

Vice President & Co-founder, Culinary Arts Club2022 to 2025

University of Massachusetts Amherst · Amherst, MAWeekly cooking sessions for 20 members, plus a Discord/Jira bot and a $17k budget.

Coordinated and hosted weekly cooking sessions, directing a team of 20 members in an industrial-grade kitchen.
Scripted a Discord bot synced to Jira Cloud to automate task handling, pushing tasks with approaching deadlines.
Mapped out a $17,000 term budget to fund club events, ensuring efficient resource allocation.

Discord APIJira Cloud